Two years ago, ST released the STM32H7 single-core product. This year, ST launched the world's most powerful dual-core product: MCU STM32H7.
Since the launch of the first generation of STM32 products in 2007, the STM32F1, ST has made breakthroughs every year based on new cores or new technologies. For example, in 2009, the ultra-low power series STM32 L1 was introduced; In the performance sequence, the first STM32F2 product line based on the 90-nanometer process was launched in 2010; this year, the world's most powerful MCU STM32H7 dual-core product was launched.
The highlights of the dual-core STM32 H7 are mainly 4 points:
(1) The most powerful, high-performance dual-core MCU: The new STM32 H7 consists of the ARM Cortex-M7 core in the ARM Cortex-M series and the ARM Cortex-M4, the best core in its class. The single core released by the former ST is based on the Cortex-M7 product. Its running score is 2400 CoreMark, and today the H7 dual-core MCU has created a new record of 3200 points of CoreMark performance. This running score is run by the Cortex-M7 2424 CoreMark. Points, plus the M4 800 run points.
(2) Flexible dual-core architecture: The powerful kernel is supported by a powerful architecture, ST's built-in Chrom-ART accelerator, and MJPEG encoder make H7 have better image display and reduce CPU workload by 90%. This will free up more CPU resources for everyone to use.
High-performance products are most likely to have problems with data transmission or increase CPU workload. The STM32H7 product family has built-in master DMA. This DMA can trigger event links. For example, you can move multiple pieces of discontinuous data to another block. In the memory, you can use the main DMA to create an event chain, let it automatically move from the memory, so that you can create a more complex task of transferring data to the memory exchange between the CPU, in this case, it is not necessary The CPU intervenes, so the CPU workload will become lighter.
The STM32 H7 new product also embeds a high-precision timer module that can generate complex PWM outputs, including all event classes, such as the Timer-triggered ADC, the ADC-triggered DAC, and the DAC back to the TIM's PWM output. The process, this high-precision process is mainly for the triggering of digital power or more complex events, and this process is carried out in the mode of setting the trigger, the CPU does not need to participate in too many event-triggered processes.
A flexible dual-core architecture that enables H7 to be used with industrial, security, and artificial intelligence applications, so how do you distribute it in applications that use a dual-core architecture? For industrial machine tools, the Cortex-M7 is responsible for the interaction of the human-machine interface, while the Cortex-M4 is responsible for communication gateway and motor control and sensor pre-processing. In terms of home automation and security, the Cortex-M7 is responsible for pattern recognition and automatic speech recognition of artificial intelligence neural networks. The Cortex-M4 is mainly divided into communication gateways and real-time interface tasks.
(3) Advanced security functions: In the data encryption and decryption part, the hardware encryption and decryption algorithm is built in, including the hash hardware accelerator. The client uses the original software to do the encryption work and becomes the internal hardware. Resources to do encryption and decryption actions can also reduce CPU workload by 90%.
(4) Rich ecosystem: In addition to the internal resources of STM32H7 described above, including its hardware configuration, we pay more attention to how developers can more easily develop STM32H7 dual-core products. From the software above, it will provide a very powerful STM32 CubeMX. The meaning of CubeMX is that it can allocate internal resources, for example, which resources will be allocated to the Cortex-M7 kernel, and which resources will be configured to the Cortex-M4 kernel. . There is also the Cube Programmer of STM32. Because the development of dual core will be the condition of two projects, the role of Cube Programmer is to merge the two projects, package them together, and turn them into a package and burn them into STM32H7 products.
On the hardware side, ST will provide three development boards, the first one is the Nucleo board, you can use it as the minimum system board, and the second one is the evaluation board. The evaluation board mainly shows key functions such as Ethernet, USB and The display part can be implemented on this board. The H7 product series supports two display interfaces, the first one is the TFT-LCD screen, the second is the MIPI-DSI screen, and the other is the version without the screen. The third is a full-featured evaluation board. This board will bring all the resources of the entire chip, and everything will be brought out for evaluation.
So what benefits does the dual-core architecture bring to everyone?
Increase system performance: H7's two processing units can work in parallel (execution of 2 tasks or one of the cores for safe operation detection), reducing computation time and average power consumption.
Increase system efficiency: Workload balancing between 3 power domains, Cortex-M7 (more powerful): GUI, DSP, security; Cortex-M4 mainly handles real-time functions such as external links, real-time systems, motor control or processes Control tasks; a large number of data acquisition modes, including sensor acquisition, general purpose input and output, and low power management.
Reduce development time: The dual-core architecture helps simplify code development and reduce dependencies between development teams; the number of parts is reduced, simplifying and shortening board design and evaluation.
Reduce system cost: More tasks can be transferred to STM32H7, which can reduce bill of materials costs. Because the integration of secondary functions does not require external devices, use one instead of two MCUs, expand the connection function, strengthen the user interface, and integrate the switching power supply. Fewer external components.
