TSMC held a technical forum yesterday. This year, TSMC's total production capacity will grow at the highest level of 7 nanometers. The second generation of EUV's 7 nanometers is expected to be mass-produced in the third quarter. This year's 7-nanometer total capacity will increase 1.5 times to reach 1 million pieces of about 12 crystals. circle. The 5nm phase has also begun to install, and is expected to be mass-produced in the first quarter of next year.

For the process technology process, Wei Zhejia, president of TSMC, pointed out that TSMC's 7-nanometer process technology was mass-produced last year. The 7-nanometer products currently seen in the market are manufactured by TSMC, and the enhanced version of 7-nm EUV has been completed. The yield is the same as the first generation of 7 nanometers; the 6 nanometer is an optimized version of 7 nanometers, the intellectual property (IP) is compatible with 7 nanometers, and the 5 nanometers have completed trial production.

Wei Zhejia said that since the development of TSMC from 28 nanometers to 7 nanometers, 7 nanometers lead the world and mass production last year. Most of the 7 nanometers currently on the market are provided by TSMC, and this season's 7 nanometer enhanced version is officially mass-produced. The 7nm optimized version of the 6nm process is also scheduled for mass production next year; the 3nm plant construction progress is already found in the land, implemented in Taiwan's development plan.

Zhang Xiaoqiang said that 7 nanometers and 6 nanometers of IP can be shared, and customers can achieve optimized product design at a lower cost. By reducing the number of masks and shortening the delivery period, it is advantageous to speed up the product launch and attract many 7nm customers.

Samsung said that it will be in the 3 nanometer overtaking, Zhang Xiaoqiang said, not commenting on competitors, but TSMC is confident that it will remain the first fab in the world to provide 5nm process OEM services next year, as for 3 nanometers. The design path and mass production time are not yet disclosed.

In the past five years, TSMC has invested nearly 50 billion US dollars to expand its production capacity. This year's capital expenditure will also maintain the original estimate of 10 billion to 11 billion US dollars. Wei Zhejia said that at present, the 5th-nanometer phase of the 18th plant in Tainan has begun to be installed. In the future, it will continue to invest in Taiwan. In addition to the 5th, 1st, 2nd and 3rd phases, 3nm has also been found.

TSMC spokesman Sun Youwen said that 5 nanometers is expected to be mass-produced in the first quarter of next year, while the 3 nanometer mass production time is not fixed, but the new technology advancement time is about 2 years, and the current 3 nanometers are progressing well, including specifications and process technologies. The definition is complete.

TSMC 2 and 5 plant director Jane Zhengzhong pointed out that this year's TSMC's total capacity will be expanded to 12 million wafers, which will increase by 2% annually. Among them, the 7-nanometer capacity will grow the most, and the second generation will join the EUV. The 7nm is expected to be mass-produced in the third quarter, and the total capacity of 7nm this year is expected to increase by 1.5 times to reach 1 million wafers.

Huawei asked TSMC to set up a supply chain in the mainland. At present, the Nanjing plant is mainly 16 and 12 nanometers. The monthly production capacity is 10,000 pieces, and it will increase to 20,000 pieces by the end of next year. There is no plan to push the process to 7 nanometers.

5nm process improvement: 45% reduction in area and 15% performance increase

At the beginning of last month, TSMC announced the launch of a full version of the 5-nanometer design architecture under the Open Innovation Platform (OIP) to help customers realize the 5-nm system single-chip design that supports next-generation advanced operations and high-performance computing applications. Targeting the 5G and artificial intelligence markets with high growth.

TSMC said that electronic design automation and silicon intellectual property leaders and TSMC have jointly developed and completed the overall design architecture through a variety of chip test vehicles, including technical files, process design kits, tools, reference processes, and intellectual property.

TSMC pointed out that the current 5nm process has entered the trial production phase, providing chip designers with a new level of performance and power optimization solutions to support next-generation high-end operations and high-performance computing applications. Compared to TSMC's 7nm process, the 5nm innovative miniaturization function provides 1.8x logic density at the core of the ARM Cortex-A72, increasing speed by 15%, and produces excellent SRAM under this process architecture. And the analogy area is reduced. It is reported that the first generation of 5nm is the second time that TSMC has introduced EUV technology, with up to 14 layers. The second generation of 7nm (expected to be used this year by Apple A13 and Kirin 985/990) has only 4 layers of EUV.

Moreover, the 5nm process enjoys the process simplification benefits provided by the ultra-violet lithography technology, and also demonstrates excellent progress in yield learning, compared to the previous generations of TSMC's processes, at the same corresponding stage. The best technology maturity.

TSMC further pointed out that the complete 5nm design architecture includes 5nm design rulebook, SPICE model, process design kit, and silicon and silicon-based verification, and fully supports proven electronic design automation tools and design processes. . Supported by the industry's largest design ecosystem resources, TSMC has intensive design cooperation with its customers, laying a good foundation for product design finalization, trial production activities and initial sample delivery.

The latest 5nm process design kits are currently available to support production design, including circuit component symbols, parametric components, circuit netlist generation and design tool technical files, which can assist in the initiation of the entire design process, from custom design, Circuit simulation, solid implementation, virtual fill, resistor-capacitance capture to entity verification and sign-off.

TSMC partners with design ecosystem partners, including Cadence, Synopsys, Mentor Graphics, and ANSYS to implement a full line of electronic design automation tools through the TSMC Open Innovation Platform Electronic Design Automation Validation Program. Verification, the core of this verification project covers the field of silicon-based electronic design automation tools, including simulation, physical implementation (customized design, automatic layout and routing), timing sign-off (static timing analysis, transistor-level static timing) Analysis), electron transfer and voltage drop analysis (gate and transistor level), physical verification (design specification verification, circuit layout verification), and resistor-capacitor acquisition.

Through this verification project, TSMC and electronic design automation partners can implement design tools to support TSMC's 5nm design rule, ensuring the necessary accuracy and improving winding capability to optimize power consumption, performance and area. Customers make full use of the advantages of TSMC's 5nm process technology.